1. Field of the Invention
The present invention relates to packaging substrates and fabrication methods thereof, and more particularly, to a packaging substrate having a through-holed interposer embedded therein and a fabrication method thereof.
2. Description of Related Art
Along with the rapid development of electronics manufacturing, electronic products are becoming low-profiled and compact-sized, as well as developed for high performance and high functionality. FIG. 1A is a cross-sectional view of a conventional flip-chip package structure.
Referring to FIG. 1A, a packaging substrate 10 having a core board 102 made of BT (Bismaleimide-Triazine) is prepared. The packaging substrate 10 has a first surface 10a with a plurality of flip-chip solder pads 100 and an opposite second surface 10b with a plurality of ball pads 101; a semiconductor chip 12 having a plurality of conductive pads 120 disposed on the first surface 10a, the conductive pads 120 being electrically connected to the solder pads 100 through a plurality of solder bumps 11, respectively; an underfill 17 used to fill the space between the first surface 10a of the packaging substrate and the semiconductor chip 12 so as to encapsulate the solder bumps 11; and a plurality of solder balls 13 mounted on the ball pads 101 for being electrically connected to another electronic device such as a printed circuit board (not shown).
Therein, when the semiconductor chip is fabricated through a process below 45 nm, its BEOL (Back-End Of Line) process requires an extreme low-k dielectric material or an ultra low-k dielectric material. However, the low-k dielectric material is porous and fragile such that in thermal cycling reliability testing after the flip-chip packaging process, a large CTE (Coefficient of Thermal Expansion) difference between the packaging substrate 10 and the semiconductor chip 12 causes an uneven thermal stress on the solder bumps 11, thereby easily resulting in cracking of the solder bumps 11 and even cracking of the semiconductor chip 12. As such, the product yield and reliability are decreased.
Further, to meet the demand for low-profiled and compact-sized electronic products, the circuit density of the semiconductor chip 12 becomes higher and pitches between the conductive pads 120 are reduced to the nano-scale. On the other hand, pitches between the flip-chip solder pads 100 of the conventional packaging substrate 10 are only at the micron-scale and cannot be effectively reduced to the nano-scale such that the conventional packaging substrate 10 does not match the semiconductor chip 12 with high circuit density, thereby adversely affecting the application of the semiconductor chip in electronic products.
To overcome the above-described drawback, a silicon interposer 14 is disposed between a packaging substrate 10 and a semiconductor chip 12′, as shown in FIG. 1B. The silicon interposer 14 has a plurality of TSVs (Through-Silicon Vias) 140, the bottom ends of the TSVs 140 are electrically connected to the flip-chip solder pads 100 with large pitch through a plurality of conductive bumps 142, and a redistribution-layer 141 is disposed on the top ends of the TSVs 140. The outermost circuit of the redistribution-layer structure 141 has a plurality of electrode pads 1410 which are electrically connected to the conductive pads 120′ of the semiconductor chip 12′ with small pitch through a plurality of solder bumps 11′. Further, an encapsulant 18 is formed to encapsulate the semiconductor chip 12′, the silicon interposer 14 and the conductive bumps 142. Therefore, the semiconductor chip 12′ with high-density conductive pads 120′ can be disposed on the packaging substrate 10 through the silicon interposer 14, thereby overcoming the physical mismatch between the packaging substrate and the semiconductor chip without changing the original supply chain and infrastructure of the IC industry.
Further, since the semiconductor chip 12′ disposed on the silicon interposer 14 has a CTE the same as that of the silicon interposer 14 (both CTEs are 2.6 ppm), cracking of the solder bumps 11′ between the semiconductor chip 12′ and the silicon interposer 14 is prevented so as to effectively increase the product yield and reliability.
Although the use of the silicon interposer 14 overcomes the mismatch between the semiconductor chip 12 and the packaging substrate 10, it leads to an increase of the thickness of the overall structure, which is against the trend of thinning the package structure.
Further, to fabricate the conductive bumps 142, the wafer needs to be ground down to 100 μm thin or thinner, which leads to a high fabrication costs due to expensive devices and materials used in such a grinding process as well as labor, thereby adversely affecting mass production of the package structure.
Therefore, it is imperative to provide a packaging substrate and a fabrication method thereof so as to overcome the above-described drawbacks.